[[ this is in the correct basket ]]
[[ this TEXT provides an example of : delay was designed to allow the recovery of the manufacturing capital equipment costs of the previous generation (256 kbits). ]]
[[ so how is this related to cycles? ]]
[[ you should see this delay in different type of businesses. ]]
Evolution of the MOS transistor ── from conception to VLSI
written by Chih-tang Sah
B. DRAM technology advances from 4 kbits to 64 kbits (1972 to 1979)
The success in the volume production of the silicon MOS integrated circuit appears to have been controlled and driven by the introduction of new technology and new production equipment [144] until about 1982 when the manufacturing technology and production planning became manture from past experiences. Since 1983, market demand and recovery of research, development, and especially production equipment and clean room costs appear to have delayed the introduction of high (finer line) technology into MOS integrated circuit manufacturing [145]─[149]. Recent delays have been caused by the production shakedown of the submicron lithography tools.
Recovery of equipment and development costs of 256-kbit and 1-4-Mbit DRAMs has become a major factor that has dictated the three-year product introduction and delivery cycle in order to make business sense. For example, during a typical recent 3-year cycle, less than 1 million chips would be shipped for sampling during the introduction year, 5 million chips for mainframes in the second production year, and over 500 million chips for personal computers and comsumer products in the third and peak production year. This trend is best illustrated using the one-transistor DRAM cell for two reasons. First, it is the largest volume product. Second, the repetitive memory structure makes it a good test vehicle to advance the silicon integrated circuit process technology since it requires the least engineering man-year to design a full memory array on a chip (with several hundred thousands to 16 million transistors on the chip today) in order to run a full-scale test of a new technology in the factory environment. However, in the last few years high density MOS logic arrays have been increasingly used as the test vehicle by some American manufacturers [150].
This huge cost further reinforces the Gordon Moore criteria: recovery of equipment and development costs is the prime consideration for the manufacturing and volume delivery of future generation of submicron VLSI and ULSI chips.
(pdf 31)
; however, the first volume product at 2500 A or shorter channel length probably will not reach the marketplace until 1995 or later due to the many necessary technology developments even if it is not further delayed by future 5-year cycles of market and economic conditions.
H. A recapulation of the Bergulund-Moore-Intel scenarios
During 1981 to 1982 when Neil Berglund gave his talks under Intel's college seminar program [144], he showed that MOS VLSI advances had been driven by the availability of manufacturing equipment and technology.
Two years later in 1983, excess production capacity from both domestic and Asian producers had turned it into a market driven business, as pointed out by Gordon Moore [145].
Profitability or the recovery of equipment investment has continued to determine the volume production and delivery dates [176],
Volume delivery of DRAM has followed a three year cycle.
, but volume delivery for personal computer use had not begun in high gear at the end of 1987 although manufacturing capacities were already in place. The delay was designed to allow the recovery of the manufacturing capital equipment costs of the previous generation (256 kbits). The delay further helps the recovery of the equipment costs to produce the current generation (1-Mbit chip) by premium initial pricing to give high profit margin before substantial price drop when volume delivery begins.
─“”
source:
Evolution of the MOS transistor ── from conception to VLSI
written by Chih-tang Sah,
____________________________________
No comments:
Post a Comment